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@@ -3,6 +3,140 @@
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#include <vector>
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+// To reduce shared memory use, store "it" and "iex_used" with 22/10 bits each.
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+struct mmq_ids_helper_store {
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+ uint32_t data;
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+
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+ __device__ mmq_ids_helper_store(const uint32_t it, const uint32_t iex_used) {
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+ data = (it & 0x003FFFFF) | (iex_used << 22);
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+ }
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+
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+ __device__ uint32_t it() const {
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+ return data & 0x003FFFFF;
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+ }
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+
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+ __device__ uint32_t iex_used() const {
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+ return data >> 22;
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+ }
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+};
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+static_assert(sizeof(mmq_ids_helper_store) == 4, "unexpected size for mmq_ids_helper_store");
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+
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+// Helper function for mul_mat_id, converts ids to a more convenient format.
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+// ids_src1 describes how to permute the flattened column indices of src1 in order to get a compact src1 tensor sorted by expert.
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+// ids_dst describes the same mapping but for the dst tensor.
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+// The upper and lower bounds for the ith expert in the compact src1 tensor are stored in expert_bounds[i:i+1].
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+template <int n_expert_used_template>
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+__launch_bounds__(ggml_cuda_get_physical_warp_size(), 1)
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+static __global__ void mmq_ids_helper(
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+ const int32_t * __restrict__ ids, int32_t * __restrict__ ids_src1, int32_t * __restrict__ ids_dst, int32_t * __restrict__ expert_bounds,
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+ const int n_tokens, const int n_expert_used_var, const int nchannels_y, const int si1, const int sis1) {
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+ constexpr int warp_size = ggml_cuda_get_physical_warp_size();
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+ const int n_expert_used = n_expert_used_template == 0 ? n_expert_used_var : n_expert_used_template;
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+ const int expert = blockIdx.x;
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+
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+ extern __shared__ char data_mmq_ids_helper[];
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+ mmq_ids_helper_store * store = (mmq_ids_helper_store *) data_mmq_ids_helper;
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+
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+ int nex_prev = 0; // Number of columns for experts with a lower index.
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+ int it_compact = 0; // Running index for the compact slice of this expert.
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+
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+ if constexpr (n_expert_used_template == 0) {
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+ // Generic implementation:
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+ for (int it = 0; it < n_tokens; ++it) {
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+ int iex_used = -1; // The index at which the expert is used, if any.
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+ for (int iex = threadIdx.x; iex < n_expert_used; iex += warp_size) {
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+ const int expert_used = ids[it*si1 + iex];
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+ nex_prev += expert_used < expert;
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+ if (expert_used == expert) {
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+ iex_used = iex;
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+ }
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+ }
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+
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+ if (iex_used != -1) {
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+ store[it_compact] = mmq_ids_helper_store(it, iex_used);
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+ }
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+
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+ if (warp_reduce_any<warp_size>(iex_used != -1)) {
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+ it_compact++;
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+ }
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+ }
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+ } else {
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+ // Implementation optimized for specific numbers of experts used:
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+ static_assert(n_expert_used == 6 || warp_size % n_expert_used == 0, "bad n_expert_used");
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+ const int neu_padded = n_expert_used == 6 ? 8 : n_expert_used; // Padded to next higher power of 2.
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+ for (int it0 = 0; it0 < n_tokens; it0 += warp_size/neu_padded) {
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+ const int it = it0 + threadIdx.x / neu_padded;
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+
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+ const int iex = threadIdx.x % neu_padded; // The index at which the expert is used, if any.
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+ const int expert_used = (neu_padded == n_expert_used || iex < n_expert_used) && it < n_tokens ?
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+ ids[it*si1 + iex] : INT_MAX;
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+ const int iex_used = expert_used == expert ? iex : -1;
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+ nex_prev += expert_used < expert;
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+
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+ // Whether the threads at this token position have used the expert:
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+ const int it_compact_add_self = warp_reduce_any<neu_padded>(iex_used != -1);
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+
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+ // Do a scan over threads at lower token positions in warp to get the correct index for writing data:
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+ int it_compact_add_lower = 0;
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+#pragma unroll
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+ for (int offset = neu_padded; offset < warp_size; offset += neu_padded) {
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+ const int tmp = __shfl_up_sync(0xFFFFFFFF, it_compact_add_self, offset, warp_size);
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+ if (threadIdx.x >= offset) {
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+ it_compact_add_lower += tmp;
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+ }
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+ }
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+
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+ if (iex_used != -1) {
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+ store[it_compact + it_compact_add_lower] = mmq_ids_helper_store(it, iex_used);
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+ }
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+
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+ // The thread with the highest index in the warp always has the sum over the whole warp, use it to increment all threads:
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+ it_compact += __shfl_sync(0xFFFFFFFF, it_compact_add_lower + it_compact_add_self, warp_size - 1, warp_size);
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+ }
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+ }
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+ nex_prev = warp_reduce_sum<warp_size>(nex_prev);
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+
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+ for (int itc = threadIdx.x; itc < it_compact; itc += warp_size) {
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+ const mmq_ids_helper_store store_it = store[itc];
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+ const int it = store_it.it();
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+ const int iex_used = store_it.iex_used();
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+ ids_src1[nex_prev + itc] = it*sis1 + iex_used % nchannels_y;
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+ ids_dst [nex_prev + itc] = it*n_expert_used + iex_used;
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+ }
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+
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+ if (threadIdx.x != 0) {
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+ return;
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+ }
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+
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+ expert_bounds[expert] = nex_prev;
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+
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+ if (expert < gridDim.x - 1) {
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+ return;
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+ }
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+
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+ expert_bounds[gridDim.x] = nex_prev + it_compact;
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+}
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+
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+template <int n_expert_used_template>
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+static void launch_mmq_ids_helper(
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+ const int32_t * __restrict__ ids, int32_t * __restrict__ ids_src1, int32_t * __restrict__ ids_dst, int32_t * __restrict__ expert_bounds,
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+ const int n_experts, const int n_tokens, const int n_expert_used_var, const int nchannels_y, const int si1, const int sis1, cudaStream_t stream) {
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+ GGML_ASSERT(n_tokens < (1 << 22) && "too few bits in mmq_ids_helper_store");
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+ GGML_ASSERT(n_expert_used_var < (1 << 10) && "too few bits in mmq_ids_helper_store");
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+
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+ const int id = ggml_cuda_get_device();
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+ const int warp_size = ggml_cuda_info().devices[id].warp_size;
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+ const size_t smpbo = ggml_cuda_info().devices[id].smpbo;
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+ CUDA_SET_SHARED_MEMORY_LIMIT(mmq_ids_helper<n_expert_used_template>, smpbo);
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+
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+ const dim3 num_blocks(n_experts, 1, 1);
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+ const dim3 block_size(warp_size, 1, 1);
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+ const size_t nbytes_shared = n_tokens*sizeof(mmq_ids_helper_store);
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+ GGML_ASSERT(nbytes_shared <= smpbo);
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+ mmq_ids_helper<n_expert_used_template><<<num_blocks, block_size, nbytes_shared, stream>>>
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+ (ids, ids_src1, ids_dst, expert_bounds, n_tokens, n_expert_used_var, nchannels_y, si1, sis1);
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+}
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+
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static void ggml_cuda_mul_mat_q_switch_type(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) {
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switch (args.type_x) {
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case GGML_TYPE_Q4_0:
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@@ -137,7 +271,7 @@ void ggml_cuda_mul_mat_q(
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ne00, ne01, ne1, s01, ne11, s1,
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ne02, ne12, s02, s12, s2,
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ne03, ne13, s03, s13, s3,
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- use_stream_k};
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+ use_stream_k, ne1};
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ggml_cuda_mul_mat_q_switch_type(ctx, args, stream);
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return;
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}
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@@ -148,53 +282,49 @@ void ggml_cuda_mul_mat_q(
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const int64_t n_expert_used = ids->ne[0];
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const int64_t ne_get_rows = ne12 * n_expert_used;
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+ GGML_ASSERT(ne1 == n_expert_used);
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- std::vector<char> ids_host(ggml_nbytes(ids));
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- std::vector<int32_t> ids_src1_host;
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- ids_src1_host.reserve(ne_get_rows);
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- std::vector<int32_t> ids_dst_host;
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- ids_dst_host.reserve(ne_get_rows);
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- std::vector<int32_t> tokens_per_expert_host(ne02);
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- std::vector<int32_t> expert_bounds_host(ne02 + 1);
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- ggml_cuda_pool_alloc<int32_t> ids_buf_dev(ctx.pool());
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-
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- CUDA_CHECK(cudaMemcpyAsync(ids_host.data(), ids->data, ggml_nbytes(ids), cudaMemcpyDeviceToHost, stream));
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- CUDA_CHECK(cudaStreamSynchronize(stream));
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-
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- for (int64_t i02 = 0; i02 < ne02; ++i02) { // expert matrices
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- for (int64_t i12 = 0; i12 < ne12; ++i12) { // tokens
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- for (int64_t iex = 0; iex < n_expert_used; ++iex) {
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- const int32_t expert_to_use = *(const int32_t *)(ids_host.data() + i12*ids->nb[1] + iex*ids->nb[0]);
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- assert(expert_to_use >= 0 && expert_to_use < ne02);
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- if (expert_to_use == i02) {
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- ids_src1_host.push_back(i12*(nb12/nb11) + iex % ne11);
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- ids_dst_host.push_back(i12*ne1 + iex);
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- tokens_per_expert_host[i02]++;
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- break;
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- }
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- }
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- }
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- }
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+ ggml_cuda_pool_alloc<int32_t> ids_src1(ctx.pool(), ne_get_rows);
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+ ggml_cuda_pool_alloc<int32_t> ids_dst(ctx.pool(), ne_get_rows);
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+ ggml_cuda_pool_alloc<int32_t> expert_bounds(ctx.pool(), ne02 + 1);
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- int32_t cumsum = 0;
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- for (int64_t i = 0; i < ne02; ++i) {
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- expert_bounds_host[i] = cumsum;
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- cumsum += tokens_per_expert_host[i];
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+ {
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+ GGML_ASSERT(ids->nb[0] == ggml_element_size(ids));
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+ const int si1 = ids->nb[1] / ggml_element_size(ids);
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+ const int sis1 = nb12 / nb11;
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+
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+ switch (n_expert_used) {
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+ case 2:
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+ launch_mmq_ids_helper< 2> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(),
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+ ne02, ne12, n_expert_used, ne11, si1, sis1, stream);
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+ break;
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+ case 4:
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+ launch_mmq_ids_helper< 4> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(),
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+ ne02, ne12, n_expert_used, ne11, si1, sis1, stream);
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+ break;
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+ case 6:
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+ launch_mmq_ids_helper< 6> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(),
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+ ne02, ne12, n_expert_used, ne11, si1, sis1, stream);
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+ break;
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+ case 8:
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+ launch_mmq_ids_helper< 8> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(),
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+ ne02, ne12, n_expert_used, ne11, si1, sis1, stream);
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+ break;
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+ case 16:
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+ launch_mmq_ids_helper<16> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(),
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+ ne02, ne12, n_expert_used, ne11, si1, sis1, stream);
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+ break;
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+ case 32:
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+ launch_mmq_ids_helper<32> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(),
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+ ne02, ne12, n_expert_used, ne11, si1, sis1, stream);
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+ break;
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+ default:
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+ launch_mmq_ids_helper< 0> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(),
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+ ne02, ne12, n_expert_used, ne11, si1, sis1, stream);
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+ break;
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+ }
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+ CUDA_CHECK(cudaGetLastError());
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}
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- expert_bounds_host[ne02] = cumsum;
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-
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- std::vector<int32_t> ids_buf_host;
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- ids_buf_host.reserve(ids_src1_host.size() + ids_dst_host.size() + expert_bounds_host.size());
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- ids_buf_host.insert(ids_buf_host.end(), ids_src1_host.begin(), ids_src1_host.end());
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- ids_buf_host.insert(ids_buf_host.end(), ids_dst_host.begin(), ids_dst_host.end());
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- ids_buf_host.insert(ids_buf_host.end(), expert_bounds_host.begin(), expert_bounds_host.end());
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- ids_buf_dev.alloc(ids_buf_host.size() + get_mmq_x_max_host(cc)); // Expert bounds are padded on device.
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- CUDA_CHECK(cudaMemcpyAsync(ids_buf_dev.ptr, ids_buf_host.data(), ids_buf_host.size()*sizeof(int32_t), cudaMemcpyHostToDevice, stream));
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- CUDA_CHECK(cudaStreamSynchronize(stream));
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-
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- const int32_t * ids_src1_dev = ids_buf_dev.ptr;
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- const int32_t * ids_dst_dev = ids_src1_dev + ids_src1_host.size();
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- const int32_t * expert_bounds_dev = ids_dst_dev + ids_dst_host.size();
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const size_t nbytes_src1_q8_1 = ne12*n_expert_used*ne10_padded * sizeof(block_q8_1)/QK8_1 +
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get_mmq_x_max_host(cc)*sizeof(block_q8_1_mmq);
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@@ -208,7 +338,7 @@ void ggml_cuda_mul_mat_q(
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const int64_t s11 = src1->nb[1] / ts_src1;
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const int64_t s12 = src1->nb[2] / ts_src1;
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const int64_t s13 = src1->nb[2] / ts_src1;
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- quantize_mmq_q8_1_cuda(src1_d, ids_src1_dev, src1_q8_1.get(), src0->type,
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+ quantize_mmq_q8_1_cuda(src1_d, ids_src1.get(), src1_q8_1.get(), src0->type,
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ne10, s11, s12, s13, ne10_padded, ne11_flat, ne12_flat, ne13_flat, stream);
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CUDA_CHECK(cudaGetLastError());
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}
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@@ -218,11 +348,11 @@ void ggml_cuda_mul_mat_q(
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// Note that ne02 is used instead of ne12 because the number of y channels determines the z dimension of the CUDA grid.
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const mmq_args args = {
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- src0_d, src0->type, (const int *) src1_q8_1.ptr, ids_dst_dev, expert_bounds_dev, dst_d,
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+ src0_d, src0->type, (const int *) src1_q8_1.get(), ids_dst.get(), expert_bounds.get(), dst_d,
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ne00, ne01, ne_get_rows, s01, ne_get_rows, s1,
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ne02, ne02, s02, s12, s2,
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ne03, ne13, s03, s13, s3,
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- use_stream_k};
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+ use_stream_k, ne12};
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ggml_cuda_mul_mat_q_switch_type(ctx, args, stream);
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}
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@@ -262,7 +392,7 @@ void ggml_cuda_op_mul_mat_q(
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ne00, row_diff, src1_ncols, stride01, ne11, nrows_dst,
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1, 1, 0, 0, 0,
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1, 1, 0, 0, 0,
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- use_stream_k};
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+ use_stream_k, src1_ncols};
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ggml_cuda_mul_mat_q_switch_type(ctx, args, stream);
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